2Megs chip on rev8 A500+ mainboard with originally 512KB chip, 256K x4 dip-20 DRAM in U20..U23:
1. Wire connecting dram A9 on all 1M x 4 modules and to buffered BDRA9 on pin 2 on U34 74F373. A9 not connected to any mainboard dip-20 pad.
2. JP3 connections disconnected, leaving U20..23 *RAS pin inactive high R202 4.7K. *CAS signals will reach these chips still, probably with no effect.
3. No U32 74F139 installed. Jumpers 4A and 4B as "originally", connecting to U35 74F244 pins 12, 14 (buffered *casu, *casl)
4. Add AND-gate (1/4 of 74F08 or so) combines active low inputs *RAS0 and *RAS1 to output *RAS for U16..U19 1M x4 modules. Pin 4 (mainboard routing connects also to n.c. pin 5 for U16..U19))
4. inputs to and gate from U35 74F244 pins 2 and 4. Output to U16..U19 pin 4. (Or other end of R201, not the +5v VCC end.)
4B. Made AND gate from two schottky diodes and extra pull-up resistor, cathode -ends from U35 74F244 pins 16 and 18. +ends together to pin 2 of RP203. Resistor 270 Ohms added in parallel with R201 4.7Kohm.
5. Workbench showed 2 Megs graphics mem. Maybe works, but to be tested more.