68060.library update

SpeedGeek

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68060.library update

LICENSE:
Copyright by Carsten Schlote 1990-2016
This release and any subsequent adapted (or non-adapted)
release is subject to all terms and conditions of the original
CC-BY-NC-BA 4.0 license release in 2016. See
http://creativecommons.org/licenses/by-nc-sa/4.0/legalcode

INTRODUCTION:
This 40.35 version of 68060.library is an update of the last
40.343 version by Carsten Schlote. This is a really good
"Generic" 68060.library with a few useful updates.

Updates (by SpeedGeek):
- Disables the Store Load/Bypass for CPU Rev. 0,1 and 5
- Some Global mappings changed to Non-Global
- Enables $E00000 Extended ROM as Cache Writethrough
- Allocates only Fast RAM for moving the VBR
- Library init code now safely exits in a 68040 system

NOTES: It works very well with TurboMMU040+ and
FastCache040+! Please understand a "Generic" library does
NOT offer support for all the features of proprietary 3rd
party accelerator cards.

REQUIREMENTS:
- Amiga with 68060 CPU and FPU

DISCLAIMER (For updates):
Use at your own risk. No warranty expressed or implied, etc.

USAGE:
- Copy to LIBS:
- OS3.1 Setpatch loads the "Dummy" 68040.library first
- OS3.9 Setpatch directly loads the 68060.library

CREDITS: Thanks very much to Carsten Schlote (Danke Schon!)

HISTORY:
v40.35 - Update release of 40.343

Here is the link:

http://eab.abime.net/showthread.php?p=1312476
 
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** NEWS UPDATE **

Changed requirements to 68060 CPU and FPU due to Mathesar's reported problem with LC060 compatibility.
 
An understandable requirement. I remember another 680x0.library developer at some point noting that an LC (no FPU) on the 040 (and translates to the 060) was pointless in an Amiga, as most code looking to take advantage of the faster FPU hardware environment expects the inline FPU code compatibility to be present, and it's just not there. You would have to emulate the entire missing F-line instruction set in exception handling (assuming it's possible). I would think a 68K-like integer-based FPU library, but with 68060-only CPU optimization, would run faster.

Also, a reminder (for all) that YMMV on the Rev 1/5 mask CPUs of EC/LC marking (and not including the China re-labeled fakes, which could be anything). They are not graded as 'full' because even though these two mask revs used the same source mask for EC and LC as the Full, they either A) didn't vet the MMU or FPU portions during production testing, or B) they were the grade-offs of the production testing where possibly some FPU or MMU functions were not 100% operational or reliable.

In the final MC qualifying, Rev 4 mask became the base of the EC060/LC060 production mask, and Rev 6 became the Full-function 060 mask.
 
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** 2ND NEWS UPDATE **
v40.36 released!

Many improvements:
- Fixed occasional crash bug in FPU dispatcher (Thanks to
Ralph Schmidt for the minor update)
- Added optimized Mult64u/s ISP patch to utility.library
functions (Much faster than exception trap code)
- Removed library versions of FPSP and ISP (Kernal versions
provide the emulation code)
- Removed lots of useless code (Debug and NOP stuff)
- Merged two library hunks into one
- Replaced Disable/Enable pairs with Forbid/Permit pairs
 
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Installed, so far so good. Will do more testing.
I deleted my old MMULib version, so I guess I no longer need disassembly.library, memory.library and mmu.library?
 
** 3RD NEWS UPDATE **

v40.37 - released!

Minor update:
- Added code to skip Library init on EC/LC060 detection
- Added code to enable branch prediction error handler
 
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