FastCache040+ Released!

** 14TH NEWS UPDATE **

FastCache040+ 2.0 released.

2.0 - Added code to enable only one DTTR when the Nest count
is one. Most systems have only one DMA driver and only need to
have 16MB of address space managed for this case.
Removed 1.9BR version which was over-rated due to most DMA
drivers operating at higher priority than typical user tasks.
 
I owe this an updated set of tests. Life has been busy of late.

With the research I did on the 68060 mask revs earlier in the year, and the known errata in the Rev 1 and Rev 5 (For the readers: Superscalar in the former, Load/Store Buffer Bypass in both) masks, you might look to check the PCR values, and have the option handy to disable those modes when those specific masks are encountered. This may give you the means to identify situations where people report instability, but may not have the tools, or understanding, to identify their chip rev/mask - not to mention fakes/relabeled chips they may have bought.

Maybe do the errata test/make the issue known only if a verbose output is desired, and also an ErrataPatch option to test and set the PCR appropriately if the user wants it.

For anyone reading this, the Ralph Babel v2.3 68060.library (for GVP/TekMagic) and the MuLibs 68060.library (Generic) were both updated in 2018 to address the Rev 5 68060 mask errata that was not identified in all earlier 68060.library revisions tested. They are the only 68060 CPU libraries to properly identify the later (but not last) masks, and set the appropriate mode(s) off. None of the other libraries have current support as of 2018 that I am aware of. This includes the 1999/2000 P5 68060.libraries. They are needed for P5 hardware, and popular/compatible for use with some modified hardware, like the A3640/A3660. The archive of the P5 libraries/tools CPU060 tool warns of messing with the modes (after their library sets them) if not knowing the results, but it's information prior to knowing about the Rev 5 mask, apparently. Some users chose to enable the library-disabled modes, thinking they should all be enabled, but then invite obscure stability problems, particularly with DMA and Shared RAM activities.
 
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I'm not going to worry too much about the Store/Load bypass bug fix (affecting certain 060 mask revisions) because I think it's fairly well supported already. If the 68060.library doesn't handle it for you than the CPU060 tool certainly will (I think the warnings are just sarcastic for users who think they can make the system faster than the P5 68060.libraries default settings).

Regarding, the TekMagic 68060.library I just discovered it suffers from the same instability problem as the P5 68060.library. It sets up Chip RAM in "Imprecise" mode and then enables the Store buffer by default. Since, I prefer to let the developer release "Official" updates I will pass this one off to Ralph. Also, I have too many "Unofficial" patches to maintain already.
wink.gif
 
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Good enough. Ralph noted to me ~2-3 weeks ago that he was swamped with some other things. I'm waiting for some utility/tools updates from him for the GuruROM distribution media. When I sorted everything down to versions, my collection was outdated for a number of them.

I happened to be helping someone else with earlier libraries, 3.9, 68060, etc, and it turned out the SuperScalar disable for the Rev 1 was very important. Also, the P5 libraries packs on A1K downloads have an older v1.6 CPU060 in the .lha that doesn't have the bypass toggle option. The standalone CPU060 in the tools subsection is v1.9 and it does have it.
 
** 15TH NEWS UPDATE **

FastCache040+ 2.1 released

v2.1 - Reworked the code to fix a problem with Snoopy 2.0 (Aminet).
Sorry, this version no longer supports 16 byte aligned cache enabled
MEMF_24BIT transfers. NOTE: The original P5 library functions have
problems with Snoopy too. I suppose FastCache040+ 2.0 should remain
available for the non-snoopers.
 
** 16TH NEWS UPDATE **

FastCache040+ 2.2 released

v2.2 - The Snoopy fix broke MEMF_24BIT transfers. So another
bug fix was required. Let's hope it's the last.
 
** 17TH NEWS UPDATE **

FastCache040+ 2.0 is no longer available and 2.2 is now the recommended version for all users. 2.2 is a little slower than 2.0 but it is also much more stable than 2.0. I was able to use 2.2 with the P5 68060.library (without FixMapP5) and there was only an occasional "Recoverable Alert" but never any hard crashing on my A3000/A3660 system.

THOR reported finding no instability problems at all with the P5 68060.library on his A2000/2060 system so there appears to be some hardware issues complicating the stability problem too. Hence, FixMapP5 is now optional and it's usage should be based the users determination of improved stability.
 
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** 18TH NEWS UPDATE **

FastCache040+ 2.4 released.

2.3 - The 16 byte alignment code is back and now avoids the
change of cache mode for this specific case. Removed
Continue case from PreDMA since the expected results are
the same as the Non-Continue case. The cache disable test
code was removed to save the overhead of this very
uncommon case.

2.4 - Reworked PostDMA code to fix Nested call cache flush bugs.
We really don't want to forget about systems with multiple
DMA drivers do we?

 
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