A500 (r6a) 1MB CHIP RAM Modification: Caution dialup users: excessive H/W pr0n!

So r6a is limited to 1MEG Chip one way or another..............

Ok.........thanks rkauer (y)


The only way to do this is to find a 500 on a rev8 board. which has already 8375 on it and is pin compatible.
 
Not true, either.

A guy made a 2Mb chip A500 rev6, check on Amiga.org. He gave the "recipe". It just require the address decoder, some cut & solder and the RAM chips.

Oh, and the 8372 Agnus (the PAL/NTSC "agnostic" one).
 
The problem is: Fatter Agnus (8375) is not pin-compatible with older Agnii.

Indeed, the 8375 3190544-xx is pin incompatible with the with the other range of Agnii

heres some more research

Code:
[B]                8375            8372             8372B          8370[/B]
              [390544-01]     [A3000]
pin#        #desc           #desc        #desc        #desc

01        DRD13        DRD13        DRD13        RD13
02        DRD12        DRD12        DRD12        RD12
03        DRD11        DRD11        DRD11        RD11
04        DRD10        DRD10        DRD10        RD10
05        DRD09        DRD09        DRD09        RD09
06        DRD08        DRD08        DRD08        RD08
07        DRD07        DRD07        DRD07        RD07
08        DRD06        DRD06        DRD06        RD06
09        DRD05        DRD05        DRD05        RD05
10        DRD04        DRD04        DRD04        RD04
11        DRD03        DRD03        DRD03        RD03
12        DRD02        DRD02        DRD02        RD02
13        DRD01        DRD01        DRD01        RD01
14        DRD00        DRD00        DRD00        RD00
15                +5V        VCC        VCC
16        _RESET        _RESET        _RESET        _RESET
17        _INTR        _INTR        _INTR        _INT3
18        DMAL        _DMAL        _DMAL        _DMAL
19        _BLISS        _BLISS        _BLS        _BLS
20        _BLIT        _BLIT        _BLIT        _DBR
21        _WE        _WE        _WE        _RRW
22        _RW        _RW        _RW        _PRW
23        _REGEN        _REGEN        _REGEN        _RGEN
24        _AS        _AS        _AS        _AS
25        _RAMEN        _RAMEN        _RAMEN        _RAMEN
26        RGA8        RGA8        RGA8        RGA8
27        RGA7        RGA7        RGA7        RGA7
28        RGA6        RGA6        RGA6        RGA6
29        RGA5        RGA5        RGA5        RGA5
30        RGA4        RGA4        RGA4        RGA4
31        RGA3        RGA3        RGA3        RGA3
32        RGA2        RGA2        RGA2        RGA2
33        RGA1        RGA1        RGA1        RGA1
34        28MHZ        28MHZ        28MHZ        28MHZ
35        A20        A20        A20        _XCLK (,A20)
36        _CDAC        _XCLKEN        NC        _XCLKEN
37        7MHZ        _CDAC        _CDAC        _CDAC
38        CCKQ        _7MHZ        _7MHZ        _7MHZ
39        CCK        _CCKQ        _CCKQ        _CCKQ
40        14MHZ        CCK        _CCK        _CCK
41                TEST        PAL/NTSC    TEST    
42        CRA0        VSS1        VSS        VSS
43        CRA1        DRA0        DRA0        MA0
44        CRA2        DRA1        DRA1        MA1
45        CRA3        DRA2        DRA2        MA2
46        CRA4        DRA3        DRA3        MA3
47        CRA5        DRA4        DRA4        MA4
48        CRA6        DRA5        DRA5        MA5
49        CRA7        DRA6        DRA6        MA6
50        CRA8        DRA7        DRA7        MA7
51        _LDS        DRA8        DRA8        MA8
52        _UDS        _LDS        _LDS        _LDS
53        _CASL        _UDS        _UDS        _UDS
54        _CASU        _CASL        _CASL        _CASL
55        CRA9        _CASU        _CASU        _CASU
56                DRA9        DRA9        _RAS1
57        _RAS0        _RAS        _RAS        _RAS0
58        _RAS1        VSS2        VSS        VSS
59        A19        A19        A19        A19
60        A01        A01        A01        A01
61        A02        A02        A02        A02
62        A03        A03        A03        A03
63        A04        A04        A04        A04
64        A05        A05        A05        A05
65        A06        A06        A06        A06
66        A07        A07        A07        A07
67        A08        A08        A08        A08
68        A09        A09        A09        A09
69        A10        A10        A10        A10
70        A11        A11        A11        A11
71        A12        A12        A12        A12
72        A13        A13        A13        A13
73        A14        A14        A14        A14
74        A15        A15        A15        A15
75        A16        A16        A16        A16
76        A17        A17        A17        A17
77        A18        A18        A18        A18
78        _LPEN        _LPEN        _LPEN        _LP
79        _VSYNC        _VSYNC        _VSYNC        _VSY
80        _CSYNC        _CSYNC        _CSYNC        _CSY
81        _HSYNC        _HSYNC        _HSYNC        _HSY
82                VSS        VSS        VSS
83        DRD15        DRD15        DRD15        DRD15
84        DRD14        DRD14        DRD14        DRD14


8375  SRC: A500 PLUS MAINTENANCE MANUAL
8372  SRC: "FATAGNUS PRESENT DANS LES AMIGA 300" .GIF
8372B SRC: "8372B-AGNUS_PIN.TXT"
8370  SRC: "8370-AGNUS-PLCC.PNG"
[CAUTION: 8372 SRC]
The schematic indicates a oblique pin plcc offset (see included picture)


FatAgnus8372.gif



Now, I believe the 8375 318069-xx is a pin compatible replacement for the 8372B (the 8372B even has the 318069-xx written on it) - these chips are on the A600 rev 1.1 and above

Interestingly on the A600 rev 1.0 "June Bug A300" its different designation on the chip. 390xxx I will take some pics.

Anyway for the most part the 8375-318069-xx I have to confirm this with the A600 specification to be 100% sure if its a 100% drop in compatible, I would suggest everyone does the same.


Now dropping in an 8372B into an A500 Rev6a *should* give it the capacity to address 2MB of chip, you will need to do some MUXING of the RAS/CAS lines, so you will need a small *fast* IC.

however this does assume ALL the angus addressing lines are on the board.


A little while ago RKauer and TheCorfiot sent me some links with some awesome info on, I shall drag these up.
 
Thanks Zetro. (y) (y) So i need 8372B. This is rare.

P.S. Please check your PM's here and there.
 
Great tutorial Zetr0! :thumbup:

I used to have a rev 6A A500, which had this mod already applied. It was a nice surprise, when I turned it on for the first time and discovered the complete meg of chip mem. I then souped it up with a 2.05 kick rom and CFIDE68k.
 
Great tutorial Zetr0! :thumbup:

I used to have a rev 6A A500, which had this mod already applied. It was a nice surprise, when I turned it on for the first time and discovered the complete meg of chip mem. I then souped it up with a 2.05 kick rom and CFIDE68k.

Thanks protek, maybe one day it may become a sticky =D

I would love to see some images with your Rev6a and the CFIDE setup - that would be great!
 
Great tutorial Zetr0! :thumbup:

I used to have a rev 6A A500, which had this mod already applied. It was a nice surprise, when I turned it on for the first time and discovered the complete meg of chip mem. I then souped it up with a 2.05 kick rom and CFIDE68k.

Thanks protek, maybe one day it may become a sticky =D

I would love to see some images with your Rev6a and the CFIDE setup - that would be great!

Here ya go:

First my old A500 with Mrmkl's CFIDE68k with 1 GB Kingston and WB 2.11. It doesn't show here but the CFIDE68k provides connection for an activity led, which I had glued in the A500's upper case. The kickstart is 2.05 (37.300). The mobo is rev 6A with 1 MB of chip (it maps the trapdoor memory as chip RAM). This particular A500 took some effort from me to get it working but it turned out pretty nicely. Unfortunately, I've passed it on to a new owner.

08102008049.jpg


Secondly, my A600 with Mrmkl's earlier CF IDE adapter, also fitted with 1 GB Kingston and OS 3.1 and 3.1 kickstart. Nowadays it has an A603 fitted. The Indivision ECS would be nice but I'm not that keen of removing the floppy.

21052008003.jpg
 
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This is the first time I have seen this tutorial and what can I say. Just WOW! Your skills ceace to amaze me Mr Z. :D

I'll have to employ you to fix all my broken Amiga's (your not 'that' far away) and pay you with tepid currys. Wachya' say? ;)
 
Make sure the currys are "imported" from Yorkshire (preferably Bradford or my mums!) cos you southerners wouldnt know a decent curry if it hit you :D

Ive yet to find a good asian takeway place down here (Im in Potters Bar with the GF at the moment, the food sucks! lol)

And Zetr0 deservers a good curry, the mans a freakin genius (y)(y)(y) I did this mod on a friends A500 (McWilly aka Alison on here :) ) and it worked a treat, and simple and easy to do, thanks Zeet!
 
I absolutely LOVE curry!!

tonight my friends Winny and Yorkie came over and I cooked a chicken Jalfrezzi Masala with chipatties =) and Pilau rice... MmMmmMmmMmmmmmMMMmmm

yes... I make it meself... well the chipatties and chicken I bought, and I cheated a little bit with some jalfrezzi paste =D

but I am really liking this payment-by-curry method =D
 
As I am too lazy to flounder in my C= books, can someone confirm me the Agnus 8372A have two CAS lines, but only one RAS?

I think that's what stops using the A501 as 512kb slow-fast RAM...
_______________

Or, pondering what I'm pondering, can other brave soul swap the CASL to CASU lines on the trapdoor pins and run a wire from Gary's A21 pin to the cut-down JP7A? This will fool the Amiga to force the trapdoor memory to act as slow-Fast while the motherboard will have the full 1Mb chip RAM.
 
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@TheoryBoy

Great Stuff (y)


@thread

Just to officially confirm, I have an 8375 - 318069-10 Agnus (2MB capable) Agnus working directly in my A2000 rev 6 (only 1MB at the moment though ;))

So this confirms its a "drop in" component for all the PLCC Agnii based machines (except A500+)


@rkauer

My friend, I do beleive the EXRAM signal (JP7A) from gary is used to bank the trapdoor port.

Because the onboard (unpopulated ram sockets) are tied to the trapdoor port to get the extra 512kb slow you would need assert a Garry Address and MultiPlex EXRAM (JP7A) for when Agnus is LOW.

Now I am pretty sure you are correct with the Agnus port not having enough RAS lines for a second 1MB - I also think that your ponder of swapping out the LCAS UCAS signals to the trapdoor port and a little A21 asert - you could get the 512KB, buuuuuut, if the lcas/ucas are not cut from the port (and then implemented with jumpwire this will cause issues with the existing 1MB of ram.

Hmmmm pondery ponders methinks =)
 
I was thinking hard on the matter last two days, and two things are known: the EXRAM signal from Gary is necessary to the Amiga know there is something hooked to the trapdoor connector, as then the Amiga puts that expansion in the slow RAM address. This is transparent to the system.

The device commonly have the same RAS & CAS lines as the Amiga chip RAM. Look in the slow RAM expansions: they all just use a multiplexer and two TTL buffers! So it's only a matter of redirecting the c00000 address to the expansion connector again after doing the 1Mb chip hack on the motherboard to have 512kb FAST RAM and activate it automagically!
 
I like what I am reading...

I wonder how that would work though with the 8370 (half meg) Agnus?
 
I think that will not work at all when using a 512kb-only Agnus. But since I have at least 3 8372A-equipped A500 here...
 
Update

because guildserver hosting is currently suspended - I have uploaded these images

The basic overview



JP2
jp2_zoom.jpg


JP7A
jp7a_zoom.jpg
 
Last edited by a moderator:
Update

because guildserver hosting is currently suspended - I have uploaded these images

The basic overview
A500_6a_1_MBCHIP.png



JP2
jp2_zoom.jpg


JP7A
jp7a_zoom.jpg


I cant see the pics :blink:
 
how strange - I ca see them here =/

heres some thumb-links (click to zoom)

Modification Diagram


JP7A


JP2


are these functioning okay?
 
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