A501 mod

rkauer

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I'm still wondering if it is possible to add the A501 as 512kb slow-RAM to an 1Mb equipped A500 (1Mb on the motherboard).

So while tinkering with the schematics, I noticed some undocumented jumpers on the A501.

Wonder if they can be hacked to fix the addressing to slow-RAM area. Any helpers? Zetr0?
 

Zetr0

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@rkauer

Good evening my friend, I just love the possibilites with the A500 - so much hackery its enough to make one giddy =D


Now, I believe that its certainly possible BUT we are going to need to do some muxing with A20 from Agnus + A21 and or EXRAM from GARY.

GARY
[pin 32]EXRAM
[pin 37]A21
[pin 38]A22​

its also worth noting that Gary's A20 [pin 36] will be in use with Agnus.

So the trick here would be to isolate the A501 when A0-A20 is being access and then BANK over to the A501 when A21[pin 37] is being used - I suspect we could use the EXRAM signal [Pin 32] - but I am still stuck on how to isolate the port -

.... ponders....

we could look and see which of the following from the Memory Expansion port is NOT connected in series with the onboard RAM

Now on the Expansion port we have

MEMORY EXPANSION
[pin 35] - _BCASL(1)
[pin 36] - _BCASU(1)
[pin 38] - _BRAS(0)
[pin 37] - _BRAS(1)​
Its quite likely we will need to modify the A501 to use one (or more of the above CAS/RAS addresses) - infact that might be all we need to do - but I suspect that we will still need to mux A21 / BCAS / BRAS and possibly A20.

I am pretty sure it could be done with one small IC.. but which lines will need some more thought and probing..

I am quite confident thinking about it now that the A501 will have to be modified - or it will just shadow the extra 512KB thats on the motherboard.
 

rkauer

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I still thinking on a simpler mod: make the board respond only to 0x00C00000 address onwards.

Notice this RAM will be only available to Workbench running from a modified boot floppy or HD as no autoconfig code is done on ROM.

Simply asserting the memory at C0000 will trigger the A21 line (IIRC) and so only doing a small re-routing of the signal instead A20 to the right spot may do the trick.

After that is just a matter of calling the memory by an addmem utility.

Of course, modifying the A500 ROM code can easy the task a lot. I'll send you a code made by Jeff to modify the memory pool to reserve an address range at boot time.
 

Zetr0

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@rkauer

That would be awesome my friend - I would like to have a lookie at the code indeed =D


now, the problem with the trapdoor port and the A501 - is going to be getting it to assert A21 for its use.... as it stands the A501 is pretty passive and relies on the Trap-door port for its address (which as you know is defaulted to C0000 on the A500)

however by performing the JP7A modification we remove that assertion

the problem is now, the Motherboard (extra) 512KB RAM and the trapdoor port are linked, how do we sever that link so that the trapdoor port doesn't just shadow whats in the upper half of chip ram?

I was thinking of modifying the port to respond to different RAS/CAS signals - thus keeping it relatively dumb and not just shadow the upper 512KB of CHIP ram, but without futher reading it would only be a guess at this point
 

rkauer

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Thing is: the expansion is dumb as a brick, but it "knowns" its size and it have a fixed relative address range. From x00000 to x80000.

My approach is sever the A20 line from the board and route the A21 line to its place to check if the board start responding at the new address range after a software mount.
 

Zetr0

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That sounds like a great plan my friend =)
 

skippy

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I was chewing on the idea of doing this some time back then concluded it would require quite a few mods so opted for the MegaChip route (REM: faulty DBK.)

I did start documenting from what reference material I had to see how much change was needed, but like rkauer, I wanted something simple and concise that anyone could easily implement without exhaustive hackery.

http://lh3.ggpht.com/_lD5TbYVyyUI/THhs8M-CfFI/AAAAAAAAGYE/MeL5vcT3KTk/Agnus2MB.jpg

It was an extension idea to my original 1MB A500 project: http://jetsetskippy.blogspot.com/2010/08/commodore-amiga-a500-1mb-chip-ram.html
 

Zetr0

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Hiyas Skippy

thats an interesting project, how do you generate Address 19 ? the 8370 Agni is a 512K CHIP Address Generation Unit, to go any higher and you would need atleast A19 - which it doesn't have.

I had this crazy idea a while back of multi-plexing Agnii together to get the full 2MB from two 1MB 8371's... then I went off to dream land and thought of multiplexting two 2MB agnii for a 4MB chip address generation unit... ... and I didn't get anything done as I was too busy in day dream land accepting my nobel prize for 4MB chip on an A500!

funny thing dreams =D


Now, I must comment on your site - skipps.. ;)

I like it.... its good, clean (in terms of not cluttered) with lots of info, but the biggest boon is that you are honest - if only there were more about like yourself =)
 

AndyLandy

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Thing is: the expansion is dumb as a brick, but it "knowns" its size and it have a fixed relative address range. From x00000 to x80000.

My approach is sever the A20 line from the board and route the A21 line to its place to check if the board start responding at the new address range after a software mount.

What's the actual issue here? I thought that the Slow-Fast and the extended Chip were at different address ranges? Is the problem that if you configure the second half of on-board RAM to be Chip then the trapdoor is shadowed to the same place?
 

Zetr0

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@Andy

with the A500 Rv6A - the trapdoor port is pathway linked (RAS/CAS/ADR) with the motherboard space for the extra 512KB of RAM - so in populating the motherboard and aserting A20 (JP2) and disabling EXRAM (JP7A) we force the location of the trapdoor socket to the Upper half of 1MB CHIP RAM space.

the same would the case if this was on the Trapdoor port (in the flavour of an A501)RAM upgrade.

So as it stands, buy putting any Adapter on the trapdoor port the memory would be shaddowed by both the card and the upper 512KB of the 1MB on the motherboard.

Rkauer is thinking of changing the address of the Trapdoor port - to do this he needs to isolate the trapdoor port from the motherboard -

This can be done by disabling A20 from the trapdoor port (not the motherboard)
Then jump wire A21 in its place on the trapdoor port.

from this rkauer should be able assert the extra ram of the trapdoor port using a simple AddMem call at such and such range.

Should that this work this would provide a basis for the addition of a lot more memory =)


okay.... now I am having Déjà vu!!!
 

skippy

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@Zetr0, those mapping notes were only to give me a pictorial overview. As you rightly pointed out that's a 512k (A1000), as I lacked schematics for other variants of the Agnii that one had to do.

Basically my blog site is there for everyone with an interest, as I learn I share my findings with others who are more than welcome to contribute, correct, etc.

I would say, as you've pointed out above, I do struggle with getting the information from my brain into a blog, so please double check everything! hehe - I get side-tracked by other projects so errors creep in on the literature. On reflection I do find what was in my head hasn't translated too well to text.

I do definately think that it's possible to achieve this goal, I simply didn't have enough information available.

As for dreamland, best place to be sometimes..

Not stating the obvious, but that shadowing of 512K simply gives the YELLOW error when you make both the onboard and trapdoor simultaneously available.
 

skippy

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Where's those Oracles Zetro and rkauer, bet they're in the Matrix... :cool:


The trapdoor is currently disabled via JP7a for 1MB motherboard; trapdoor addr$ assertion removed.

* ADDMEM call the necessary multiplexed RAM address.

* RAS1 and CAS1 [Expansion Port] w/ multiplexed RAM Addr$ HOOKED to "new allocated addr$ assertion" assigned to TRAPDOOR.

* Listen for access [A21] Pin 37 GARY and point to TRAPDOOR ONLY IF address of new assertion ELSE upper CHIP RAM.

(As RAS1 is tied in with the motherboard via JP7a it will be pointing to the upper CHIP RAM onboard.)


(You won't be able to use the EXRAM signal as that is routed to the upper CHIP RAM onboard so again an assertion is needed.)

RAS1+CAS1+Multplexed addr$-->MUX (listen/hook with pin37/EXRAM)-->TRAPDOOR.

Metering the signals with an oscilloscope would be useful too.

As you've mentioned the need to isolate and HOOK the requested address and the theory would be use a suitable (decoder/ demultiplexer / PIC)
that listens for these requests to be re-routed.

At the moment I'm wondering at how this modification affects the synchronous and asynchronous mode signals from the 68000 and its relationship with the External Address Decoder/Valid (peripheral) Address/Bus, but as the modification is addressing $C00000 and it's within the hierarchy layout it should be ok after all it should be seeing and addressing it a FAST RAM.


An obvious disadvantage of this mod is the trapdoor 'Slow Fast RAM' access time is slower as it's done through the Custom chip data bus. (Unless you want to go completely nuts and bolt on a DMAC and addr$ the trapdoor as $200000, but that renders the side expansion useless for memory access.)

It would be nice to find a solution as this would allow both the upgrade mod of a 1MB CHIP RAM onboard and utilisation of the trapdoor
expansion, that is currently made redundant.

Who the hell meters an A500 at this hour - heheh :D
 

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skippy

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I'm wondering if the best option would be to replaced/modified U35 [74F244N] as this acts as the gateway between the onboard RAM/Trapdoor determined by the CAS/RAS signals. It would also give greater control and flexibility when addressing memory. :blink:

Be quite a feat though mapping out the logic gates... oh is that my bed calling me - :run:
 

rkauer

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Again: why going nuts with autoconfig for 512kb of RAM? Making a programmed controller can be awesome, but not intrinsically necessary.

A simple cut & solder plus asserting the line via software will do the trick nicely, as that ¹/2Mb will be used only for WB/WHDLoad.

The slow-fast address (C00000 to C7ffff) is only used by this kind of expansion, anyway.

Making it available to all Amiga programs then will involve more serious hackery (like calling the memory from ROM, another easy hack).
 

Zetr0

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Thats some good reasearch Skippy!

I think in terms of multi-plexing a simple 74F138 would do when using the right signals.

so - lets look at the latching RAM controller of the A500 - U35
 

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Zetr0

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@rakuer / skippy

If you notice there are 2 inputs and 2 outputs not in use on the F244 (U35)

I suspect with a little play one could route these as extra RAS lines - RAS 2 and RAS 3 - thus routing outputs of 1Y2 and 1Y3 to the RAS 0 and RAS 1 of say an A501 (and or A501+)

you would

1. need to pickup/generate a RAS signal - pump it to U35 1A2 - pickup the result 1Y2 and then throw it at MEXP (Memory EXpansion Port) RAS0 and RAS1 - you will need to make sure that these signals (RAS0 and RAS1) are isolated from the motherboard though.

the best way to look at this is like just adding another block or bank of RAM - I have an idea - if I get time I will scribble it down.
 

rkauer

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Ohhhhhhhhh. :)

The plot thickens!
b16078381.gif
 

skippy

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This can be done by disabling A20 from the trapdoor port (not the motherboard)
Then jump wire A21 in its place on the trapdoor port.

@Zetr0: Would you do me a favour when you've got time, as I lack alot of the schematics, and show me where A20 is on the trapdoor and how this works.

@rkauer " Again: why going nuts with autoconfig for 512kb of RAM?" - I just thought it seemed a nicer idea :unsure:

"Making it available to all Amiga programs then will involve more serious hackery (like calling the memory from ROM, another easy hack)." - I'm a bit rusty but don't Libraries take care of that? Now I'm waiting for a :hammer:

I think we have two concept ideas running parallel at the moment.

Right, I'm having my Asda Branflakes and a cuppa tea :LOL:
 

skippy

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I'm currently working from these Rev 5 motherboard schematics found at the back of the A500 User Manual.
 

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skippy

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So while tinkering with the schematics, I noticed some undocumented jumpers on the A501.

Those JPx seem to be only on the Rev6 board, I'd be interested to know what they do, but I don't want to remove the RF shield from mine.

http://amiga.resource.cx/photos/photo2.pl?id=a501&pg=1&res=med&lang=en

JP2 and JP3 seem to be tied in with the Logic Gates to Memory Banks and JP9 (SIL) resistor RP903. JP1 looks as though it's connected to Pin 15 of trapdoor which is DRD-15 to DATA Paths U10-13.

Do you expect me to talk? No Mr Bond, I expect you to die!
 
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