Omega Projects 14mhz 68k Hack

Zetr0

Ya' Like it Retr0?
Joined
Nov 22, 2007
Posts
9,900
Country
UK
Region
Norfolk
Hello there my fellow AmiBayers

A while back I got a small 14mhz Omega Projects board

omega14k.jpg


now it had taking a smidge of damage in storage, (some of its wires were snipped and not completely soldered at the other end)

I have repaired the unit and would like to give this a little try out within an A500+

I am trying to source a 28mhz clock, the Agni is a firm no as its socketed, I have checked both Gary and Denise and they only have a 7hz clock

so any ideas?
 

TheCorfiot

Out in the Wild
VIP
Joined
Mar 28, 2008
Posts
8,698
Country
Greece
Region
Corfu
Zetr0

I would solder a flylead on the underneath of the board from the AGNES socket my friend and feed it over to the top.
No doubts it is also available via a through track pinhole from top to bottom too but I don't have access to the track layouts.

Refer to the downloaded schems to find the pin number of the 8375 socket being fed the 28MHz clock.

Sound's interesting & I hope you get it working..

TC :)
 

TheCorfiot

Out in the Wild
VIP
Joined
Mar 28, 2008
Posts
8,698
Country
Greece
Region
Corfu
Okey Dokey...lets have a better lookie

Pin 12 of U33 will deliver the 28Mhz Clock or....

my preferred however is to find capacitor E666 (ceramic type), 1 side will be GND the other will be............you guessed it 28MHz Clock :p


Hope that helps my friend

TC :LOL:
 

Attachments

  • AGNUS_CLK.jpg
    AGNUS_CLK.jpg
    51 KB · Views: 1

Zetr0

Ya' Like it Retr0?
Joined
Nov 22, 2007
Posts
9,900
Country
UK
Region
Norfolk
@TC

Your help has been invaluable my friend,

Initiall I removed the onboard OSc and placed some nice gold-turned pins - thus socketing the 28mhz Osc,

I attempted the following

Direct from the 28mhz CLK of the osc -
this didnt work, infact the A500+ wouldnt even boot with the switch ON/OFF

Soldering a small catchment on Pin 34 of the Agnus
Again, complete failure, no boot at all in either postition.

E666 (either side of the cap)
7Mhz boot would not boot with 14mhz switched on

U33 (Pin 12)
7Mhz boot - wouldn't boot with 14mhz switched on


Well my next try is to see if i can source a 14mhz CLK, I know there is one on PIN 40 of the Agnus, i may just tack a bit of jump wire there..

my thanks my friend, its been an interesting evening, with soldering, de-soldering and hackery....mmmmm just love hacking =D
 

r0jaws

Mondeo Man
Joined
Jan 23, 2008
Posts
7,237
Country
UK
Region
Lincolnshire
Good to see you having a crack at this buddy, I could never get it to work in my 2000.
Would be nice with a smidge of RAM on the side. ;)
 

Zetr0

Ya' Like it Retr0?
Joined
Nov 22, 2007
Posts
9,900
Country
UK
Region
Norfolk
Update

I decided to plumb up the 14mhz signal from Agnus [pin 40] to the adapter, results were interesting,

in either setting the unit booted and sysinfo clocked in at 7.09 mhz -

this is what one could expect with the clock devisor on the adapter (i.e halving 28mhz to 14mzh or in the above 14mhz to 7mhz)

So here's some much deserved late night pr0n

Click to enjoy close-up ;)



Click to enjoy close-up ;)



my plan in a bit is to grab a cupa and see if I can plumb in the 68k directly into the 14mhz from Agnus.





XOR forgive me!!!!
 

Zetr0

Ya' Like it Retr0?
Joined
Nov 22, 2007
Posts
9,900
Country
UK
Region
Norfolk
Good to see you having a crack at this buddy, I could never get it to work in my 2000.
Would be nice with a smidge of RAM on the side. ;)

indeedy!!!

see your up late my friend, been delving into lots of hackery, It would be nice if i can get this to boot in 14mhz -

I know there will likely be timing issues with XOR'ing back down to the 7Mhz bus, but I did a design based on a more advanced method that XOR'd back to the bus using EClock and CDAC.

worse case scenario, if either the divisor is not capable of taking a 28mhz clock rate then I have a 16mhz compatable 680000 cpu and headers for a more advnaced board =D
 

Zetr0

Ya' Like it Retr0?
Joined
Nov 22, 2007
Posts
9,900
Country
UK
Region
Norfolk
Have a final update

I decided to disconnect the Clock line on the adapter and plum 14mhz direct from the 8375 3190544 Angus (pin 40)

(For those reading at home - this is not the same as the 8375 318xxx series!!! you have been warned! these chips are NOT pin compatible)

(click for a stupidly large picture!)


(click for a stupidly large picture!)


(click for a stupidly large picture!)



So what happned ?


well it works =D.... 14 m e g a h e r t z!!!!



Although, it is incompatible with the GVP A500HD+ (hence no fast ram or harddisk!) - having this attached - even in game mode - leaves you with a yellow screen of non-functiony-ness!!!!

It can boot a workbench disk, although its fun to see that little floppy on the boot screen wizz about into the drive....

Alas, as I suspected this *hack* cannot function without extra circuitry when in use with Fast RAM (will discuss XOR'ing in the next lession =D)


All in all a great nights fun - lots of hardware pr0n to share, got to geek out with me guys and perform lots of A500+ hackery =D
 

TheCorfiot

Out in the Wild
VIP
Joined
Mar 28, 2008
Posts
8,698
Country
Greece
Region
Corfu
Very nice in deed Z

From what you described above in your post 4 using the 28MHz clock, It suggests the Clock divider IC on the Turbo PCB is up the spout my friend. you have confirmed this by applying 14Mhz directly to the 68K's Clock i/p.

I'm not 100% sure but I don't think the 14Mhz output by AGNUS is as pure as simply dividing the system clock by 2.

We need to change the chip & check the tracking on the Turbo board as I think it would be better to use the intended system 28MHz clock to ensure all phases & widths are maintained.

Nice going though (y)

TC :bowdown:
 

r0jaws

Mondeo Man
Joined
Jan 23, 2008
Posts
7,237
Country
UK
Region
Lincolnshire
Good work fella! Softly softly catchy monkey. :D

I was indeed upto hackery mischief last night, although I was also only partially successful, expect updates.
 

Zetr0

Ya' Like it Retr0?
Joined
Nov 22, 2007
Posts
9,900
Country
UK
Region
Norfolk
@TC

heres my antithesis on the 14mhz Omega Projects Adapter =D

Very nice in deed Z

From what you described above in your post 4 using the 28MHz clock, It suggests the Clock divider IC on the Turbo PCB is up the spout my friend. you have confirmed this by applying 14Mhz directly to the 68K's Clock i/p.

I'm not 100% sure but I don't think the 14Mhz output by AGNUS is as pure as simply dividing the system clock by 2.

We need to change the chip & check the tracking on the Turbo board as I think it would be better to use the intended system 28MHz clock to ensure all phases & widths are maintained.

Nice going though (y)

TC :bowdown:


The Omega Projects adapter only has one IC -a F74: Dual Type - Positive Edge - Flip Flop

The switch just changes powers on the IC, thus the 7m clock is stoped and the 28mhz is then thumped to the CPU every other tick (hence 14mhz)

there is NO buffering or XORing or cycle timing for the Eclock or 7mhz bus, hence ANY adapter that requires CPU latching time is NOT going to work.

I had a theory that this adapter had some serious short commings - when I designed a 14mzh board for the A600 (based on Livio Plos's schemaitc) I came up witrh the Musashi Turbo board.

The work was based on Livo Plos's schematic - this included proper signal buffering and appropriate waits and timing cycles -

ACCEL.jpg


(for those at home, it looks more complicated than it is)

here is a parts list -

Code:
Parts  List:

U1         68000/16 (or /12 see text)
U2         74LS74
U3         74LS27
U4         74LS86
U5         74LS112A
U6         old 68000 socket (see text)
Very common components =D

heres the All important NET LIST

Code:
[COLOR=SeaGreen][B]Signal Name     IC&PIN number   IC&PIN number[/B][/COLOR]

A1                  U1(32),         U6(29);
A2                  U1(33),         U6(30);
A3                  U1(34),         U6(31);
A4                  U1(35),         U6(32);
A5                  U1(36),         U6(33);
A6                  U1(37),         U6(34);
A7                  U1(38),         U6(35);
A8                  U1(39),         U6(36);
A9                  U1(40),         U6(37);
A10                 U1(41),         U6(38);
A11                 U1(42),         U6(39);
A12                 U1(43),         U6(40);
A13                 U1(44),         U6(41);
A14                 U1(45),         U6(42);
A15                 U1(46),         U6(43);
A16                 U1(47),         U6(44);
A17                 U1(48),         U6(45);
A18                 U1(49),         U6(46);
A19                 U1(50),         U6(47);
A20                 U1(51),         U6(48);
A21                 U1(53),         U6(50);
A22                 U1(54),         U6(51);
A23                 U1(55),         U6(52);
D0                  U1(5),          U6(5);
D1                  U1(4),          U6(4);
D2                  U1(3),          U6(3);
D3                  U1(2),          U6(2);
D4                  U1(1),          U6(1);
D5                  U1(68),         U6(64);
D6                  U1(67),         U6(63);
D7                  U1(66),         U6(62);
D8                  U1(65),         U6(61);
D9                  U1(64),         U6(60);
D10                 U1(63),         U6(59);
D11                 U1(62),         U6(58);
D12                 U1(61),         U6(57);
D13                 U1(60),         U6(56);
D14                 U1(59),         U6(55);
D15                 U1(58),         U6(54);
FC0                 U1(30),         U6(28);
FC1                 U1(29),         U6(27);
FC2                 U1(28),         U6(26);
BR*                 U1(13),         U6(13);
BG*                 U1(11),         U6(11);
BACK*               U1(12),         U6(12);
IPL0*               U1(27),         U6(25);
IPL1*               U1(26),         U6(24);
IPL2*               U1(25),         U6(23);
7M                  U4(1),          U4(4),
                    U6(15);
Line#1              U2(2),          U3(12);
7M*                 U4(6),          U2(11),
                    U2(3);
BERR*               U1(24),         U6(22);
RES*                U1(20),         U6(18);
HALT*               U1(19),         U6(17);

[COLOR=Purple][B]Signal Name     IC&PIN number   IC&PIN number[/B][/COLOR]

R-W                 U1(9),          U6(9);
UDS*                U1(7),          U6(7);
LDS*                U1(8),          U6(8);
Line#2              U2(9),          U3(2);
DTACK*out           U1(10),         U2(6);
DTACK*              U3(1),          U6(10);
AS*                 U4(9),          U1(6),
                    U2(12),         U6(6);
CDAC                U4(2);                     {see documentation}
AS                  U4(8),          U2(1),
                    U2(10),         U5(14);
E14                 U4(12),         U1(22),
                    U3(4),          U5(1);
E                   U3(3),          U5(5),
                    U6(20);
VPA*                U3(5),          U6(21);
Line#3              U3(6),          U5(11);
VMA*                U1(23),         U5(7),
                    U6(19);
E14*                U4(11),         U5(13);
14M                 U4(3),          U1(15);

[COLOR=Red][B]Power Plane:  +5V[/B][/COLOR]
  U5(16),           U3(14),         U2(14),
  U2(14),           U4(14),         U1(52),
  U6(52),           U1(14),         U6(14),
  U4(13),           U5(10),         U5(15),
  U5(4),            U5(3),          U5(2),
  U2(4),            U4(10),         U2(13),
  U4(5);

[B]Ground Plane: +0V[/B]
  U5(8),            U3(7),          U2(7),
  U4(7),            U1(57),         U6(57),
  U1(56),           U6(56),         U1(17),
  U6(17),           U1(16),         U6(16),
  U5(12),           U3(13);
A nice sundays work with a bit of bread board and a jumper-wire frenzie =D


Livio Plos explains in detail the short commings of the brute-force 14mhz approach like the Omega Projects adapter in his project - which you can download here for more reading.

He continues to point out the failing of the brute force methods not taking into acount inverse timing signals and bus negotiation signals. I have to admit, with the experience here and the reading of his work, I am very inclined to agree with him.

I Have all the needed IC's and I have a theory that this Sunday will bring about a nice moment of 14mhz hackery. =D

for those at home you can download Livio Plos's Accelerator project here



Good work fella! Softly softly catchy monkey. :D

I was indeed upto hackery mischief last night, although I was also only partially successful, expect updates.

This is relevant to my interests, where might i subscribe? =D
 

Kin Hell

Active member
Banned
Joined
Nov 25, 2007
Posts
6,970
Country
U.K.
Region
Cornwall
@ SdG

You're not on your own. :huh:
All I can say it's a good job we all have different sized lumps on the sides of our heads. :nod:

Kin
 

Merlin

Ministry of Retr0bright and Street Judge
VIP
Joined
Nov 24, 2007
Posts
15,597
Country
UK
Region
Manchester
If it's hardware pr0n, I'm in......;)
 

Tajmaster

Truth, Justice, all that stuff.
Joined
Sep 16, 2009
Posts
5,289
Country
UK
Region
Bradford, West Yorkshire
As Im thick, please can you explain what this is? Is it an attempt to connect a faster 68000 CPU to the A500/+/2000? Sorry for the n00b question :oops:
 

Zetr0

Ya' Like it Retr0?
Joined
Nov 22, 2007
Posts
9,900
Country
UK
Region
Norfolk
I love you guys

ericcartman.jpg



Seriously Taj / SdG I lol'd

:grouphug::grouphug::grouphug:


@Taj

this thread originally was about sourcing a 28mhz frequency from the A500/A500+

This then would be fed to an compatible 68000 cpu, taking it from 7mhz to 14mhz.

Although this works, it has problems, as the recycle time (thats the timing of the CPU) is all off beat and things like adapters (A500HD+) cannot function.

The thread then focuses on why this doens't work (yeah, I kinda got a little geeked out there, sorry for that) and proposes a method that would allow for 14mhz and to re-engineer timings so that adpaters could work propely...

so in short.... yes... this is souping up the 68k cpu, which is quite a MIP munching monster when unleashed!!!

(a 28mhz 68000 cpu is about the same speed of an 020@14)

its also because one can =D
 

Tajmaster

Truth, Justice, all that stuff.
Joined
Sep 16, 2009
Posts
5,289
Country
UK
Region
Bradford, West Yorkshire
I love you guys

ericcartman.jpg



Seriously Taj / SdG I lol'd

:grouphug::grouphug::grouphug:


@Taj

this thread originally was about sourcing a 28mhz frequency from the A500/A500+

This then would be fed to an compatible 68000 cpu, taking it from 7mhz to 14mhz.

Although this works, it has problems, as the recycle time (thats the timing of the CPU) is all off beat and things like adapters (A500HD+) cannot function.

The thread then focuses on why this doens't work (yeah, I kinda got a little geeked out there, sorry for that) and proposes a method that would allow for 14mhz and to re-engineer timings so that adpaters could work propely...

so in short.... yes... this is souping up the 68k cpu, which is quite a MIP munching monster when unleashed!!!

(a 28mhz 68000 cpu is about the same speed of an 020@14)

its also because one can =D

You (and I must say quite a few other on here) are one clever dude (y) And thanks for putting it in muppet speak for me ;) lol

I remember reading somewhere that the 68000 CPU was the most developed of the 68k line so if you get this going you might be able to use an even faster 68000 :p
 

rkauer

Amiga fanboy
Joined
Dec 17, 2007
Posts
10,337
Country
Brazil
Region
São Leopoldo, RS
One thing that causes this brute force project fail is the fact that on the A500 the E-clock is given by the 68000 itself: it is a decade divider of the clock the 68000 receives (7.09MHz -> 709kHz).

The E-clock is used by the CIAS.

Guess what happens when they receive the expected clock multiplied by ten?:banghead:
 
Last edited:

SkydivinGirl

Retro Girl
Joined
Dec 16, 2008
Posts
7,069
Country
USA
Region
Raleigh, NC
I love you guys

Seriously Taj / SdG I lol'd

:grouphug::grouphug::grouphug:
I'm glad you took my misguided attempt at humor for what it was. :) I love to see your passion in posts like these. :D

Heather
 
Top Bottom