For Sale A500 IDE adapters, PS/2 mouse adapter, A600 CF adapter
- Thread starter mkl
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1stFalloutboy
New member
Hi, I know this is out of context and I apologize to the moderating gods in advance if I am not allowed to ask but how are these for reliability, do they support master/slave and what is the largest IDE you can run on one?
Short answer: should be the same as with A600 ide, master/slave, 4gb max without extra drivers (the board emulates 600 ide)
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TV-frequency-VGA-in+stereo-in -> SCART-socket-connector-out
https://www.amibay.com/showthread.php?92367-VGA-to-SCART-adapter-boards
- - - Updated - - -
TV-frequency-VGA-in+stereo-in -> SCART-socket-connector-out
https://www.amibay.com/showthread.php?92367-VGA-to-SCART-adapter-boards
Last edited:
TheMightyMadman
Member
Hi again,
My first board arrived safely and I'm looking forward to using it, thank you!
What's the availability of an A500 8MB RAM/IDE combo board, plus a cut-down CF adaptor? Thanks
My first board arrived safely and I'm looking forward to using it, thank you!
What's the availability of an A500 8MB RAM/IDE combo board, plus a cut-down CF adaptor? Thanks
A few v65 ram boards left.
I've learnt from the Terriblefire videos in some Amigas the 7MHz clock noise can false clock the cplds. I'm getting an oscilloscope to look at it, using different A500 and one B2000 mainboards. 68000 Amigas differ a little bit how these signals come to 68000 socket. According to schematic A1000 7Mhz comes from ttl chip 74S51 through ferrite bead. In a500 from fat agnus through 22(?) ohm resistor. A500 plus schematic also shows 47pF termination capacitors for clock signals.
I'm putting a reset line 'filter' to cpld code. This signal's rise time can be slow with pull-up resistor and some imagined nanosecond noise glitch could false reset fast responding pld.
I've learnt from the Terriblefire videos in some Amigas the 7MHz clock noise can false clock the cplds. I'm getting an oscilloscope to look at it, using different A500 and one B2000 mainboards. 68000 Amigas differ a little bit how these signals come to 68000 socket. According to schematic A1000 7Mhz comes from ttl chip 74S51 through ferrite bead. In a500 from fat agnus through 22(?) ohm resistor. A500 plus schematic also shows 47pF termination capacitors for clock signals.
I'm putting a reset line 'filter' to cpld code. This signal's rise time can be slow with pull-up resistor and some imagined nanosecond noise glitch could false reset fast responding pld.
